With the rapid development of modern electronic technology, the feature sizes of Metal Oxide Semiconductor (MOS) devices decrease to nanometer, and the area percent of metal interconnects becomes larger and larger in the whole IC chip. The problem of EM failure in metal interconnect has become bottleneck for the development of large-scale integrated circuit (IC). The EM is the transport of material caused by the movement of electrons acting on metal atoms in the metal interconnect, which is shown as cavity or hillock, which causes resistance value increase linearly resulting in failure, and which seriously influences the life of IC. The factors that affect EM in metal interconnect are very complicated, including work current crowding, joule heat, temperature gradient, crystal structure, crystal orientation, interface microstructure, stress gradient, alloy composition, size and shape of interconnect, etc. Especially, under the action of higher current densities, metal atoms in the metal interconnect are more likely to cause EM along the direction of electron motion.
At present, there mainly exist two approaches to achieve the prediction and protection for reliability of MOS device: one is carrying out reliability life test for MOS device and predicting the reliability life of the device, and the other is performing failure analysis for a MOS device, determining its failure mode and failure mechanism, and proposing improvement measures based on this.
However, for the first of the above approaches, the reliability life of a MOS device is calculated by the reliability life test data based on simple stress condition, and actual working state and working environment are not involved in the reliability life test, while in practical use, the MOS device is in a complicated working environment under the comprehensive effects of various stress, so a traditional life prediction is quite different to reality, with poor reliability. In addition, such reliability prediction for MOS device costs a lot of money and time and needs to be tested regularly.
For the second of the above approaches, failure analysis of a failure device is a post diagnosis technology, which is not a best approach from both economy and technology standpoints for a device with very clear failure mode and failure mechanism.